Nanomaterials in Nanoelectronics

SUMMARY

MOTIVATION

As semiconductor devices are scaled to smaller and smaller sizes within thenanoregime, a variety of technological and economic problems arise, the rules ofclassical physics give way to quantum mechanics, and the term molecular-scaleultimately becomes as or more accurate than nanoscale. At this point, the sizescaling that has successfully taken device features from the microscale to thenanoscale can no longer be continued, and alternative manufacturing methods,materials, device structures, and architectures are required.

In this regime,molecular and nanostructured materials are combined with existing and emergingprocessing technologies to fabricate nanoelectronic devices and interconnectsthat promise continued miniaturization and performance enhancement innext-generation memory and logic chips.

STUDY GOAL AND OBJECTIVES

Specific objectives of this report are to:

• Explain the scaling limitations facing the semiconductor industry;
• Provide a historical timeline of major developments in the nanoelectronicsfield;
• Identify the major and minor players in nanoelectronics development inindustry and academia;
• Conduct a thorough search of the U.S. patent literature, and identifytrends and technology leaders;
• Identify the nanoelectronic materials, devices, and architectures incontention for future memory and logic chips;
• Describe the relevant fabrication methods, including existing and emergingprocessing technologies;
• Determine the requirements for developing and commercializing these newnanoelectronic technologies;
• Evaluate their potential impact and commercial feasibility; and
• Propose a time frame and roadmap for commercialization.

SCOPE AND FORMAT

This report covers the gamut of emerging nanoelectronic memory and logicdevices, including carbon nanotube memories, molecular electronic memories,semiconductor nanowire memories, silicon nanocrystal memories, and spintronicmagnetic random access memory (MRAM). Also covered are carbon nanotube andsemiconductor nanowire field effect transistors (FETs), quantum dot-based singleelectron transistors (SETs), molecular electronic switches, and new logicarchitectures, including programmable logic arrays and quantum dot cellularautomata. Quantum computing, a futuristic computing approach that relies onmultistate qubits in lieu of binary ones and zeros, is outside the scope of thisreport.

The report begins with an Overview chapter that provides neededbackground about trends in semiconductor technology, device scaling challengesand short-term solutions, as well as a chronology of major events in thenanoelectronics field during the past several decades. The Industry Structurechapter identifies and profiles major and minor players in the nanoelectronicsbusiness and also covers U.S. government, academic, and international researchand development efforts. The Technology chapter reviews the nanomaterials andprocessing technologies required for next-generation nanoelectronic devicetechnologies, and presents a detailed patent analysis. The final chapters take adetailed look at the materials, structures, fabrication methods, challenges,requirements, and new developments for next-generation nanoelectronic devices,evaluate the feasibility of the various technologies, and propose acommercialization roadmap.

CONTRIBUTIONS OF THE STUDY AND AUDIENCE

This seminal report evaluates the impact of the technologies and materialsthat will enable next-generation nanoelectronic devices and lays out a roadmapfor future developments.

This study is a valuable resource for executives,technical managers, consultants, and other decision-makers involved orinterested in semiconductor manufacturing, nanomaterials development, or in thecommercialization of new nanofabrication technologies.

METHODOLOGY AND INFORMATION SOURCES

The information and analyses contained in this report are based on bothprimary and secondary sources of information. Over a dozen interviews withparticipants from industry and academia were conducted by telephone and E-mail,and other information was gleaned from the U.S. Patent and Trademark Officeonline database, company press releases and websites, and scientific and tradeliterature.

TABLE OF CONTENTS

INTRODUCTION

• MOTIVATION
• STUDY GOAL AND OBJECTIVES
• SCOPE AND FORMAT
• CONTRIBUTIONS OF THE STUDY AND AUDIENCE
• METHODOLOGY AND INFORMATION SOURCES
• ABOUT THE AUTHOR
• RELATED BCC REPORTS
• RELATED BCC MONTHLY NEWSLETTERS
• BCC ONLINE SERVICES

EXECUTIVE SUMMARY

• Summary Table:
  POTENTIAL MARKET FOR NANOELECTRONIC MEMORY AND LOGIC PRODUCTS, 2003-2013 ($BILLIONS)
• Summary Figure:
  POTENTIAL MARKET FOR NANOELECTRONIC MEMORY AND LOGIC PRODUCTS, 2003-2013 ($BILLIONS)

OVERVIEW

• MOTIVATION
  • MOORE'S LAW AND ITS IMPLICATIONS
• Table 1 INCREASE IN TRANSISTORS PER CHIP BY YEAR
• Figure 1 MOORE'S LAW ILLUSTRATED
• Table 2 PROJECTED CHANGE IN CRITICAL FEATURE SIZES OF INTEGRATED CIRCUITS,2002-2016 (NM)
  • CURRENT TRANSISTOR TECHNOLOGY
  • Scaling Limitations
• Table 3 OBSTACLES TO CONTINUED TRANSISTOR SCALING
• Figure 2 IMPACT OF DOPANT DISTRIBUTION AT DIFFERENT SIZE SCALES
  • Economic Obstacles
  • CURRENT MEMORY TECHNOLOGY
  • Scaling Limitations
  • SHORT-TERM SOLUTIONS
  • Transistors
• Table 4 TECHNOLOGIES LIKELY TO EXTEND CONVENTIONAL TRANSISTOR TECHNOLOGY
  • Memory
  • ENTER NANOELECTRONICS
  • Timeline of Major Developments
  • Timeline of Major Developments (Continued)
• Table 5 TIMELINE OF IMPORTANT EVENTS IN THE DEVELOPMENT OF NANOELECTRONICS

INDUSTRY STRUCTURE

• INDUSTRY OVERVIEW
  • WHO'S WHO
  • A Close Look at the Start-Ups
• Table 6 WHO'S WHO IN THE NANOELECTRONICS BUSINESS
• Table 7 COMPARISON OF NANOELECTRONICS START-UP COMPANIES
  • COMPANY PROFILES
    • SMALL START-UP FIRMS
    • California Molecular Electronics Corp.
    • California Molecular Electronics Corp. (Continued)
    • Coatue Corp.
    • MITRE Corp.
    • Molecular Electronics Corp.
    • NanoInk, Inc.
    • Nanonex Corp.
    • Nanosys, Inc.
    • Nantero, Inc.
    • Quantum Logic Devices
    • Rolltronics
    • Thin Film Electronics ASA
    • ZettaCore, Inc.
    • MAJOR GLOBAL COMPANIES OR CORPORATE LABORATORIES WITHNANOELECTRONICS EFFORTS
    • Fujitsu Laboratories Ltd.
    • Hewlett-Packard Laboratories
    • Hitachi Ltd.
    • Hitachi Advanced Research Laboratory
    • Hitachi Cambridge Laboratory
    • IBM T.J. Watson Center
    • Infineon Corp.
    • Motorola Labs
    • Samsung Advanced Institute of Technology
    • Texas Instruments
  • U.S. GOVERNMENT INVOLVEMENT
    • DARPA'S MOLETRONICS PROGRAM
• Table 8 PARTICIPANTS AND PROJECTS IN DARPA'S MOLETRONICS PROGRAM
  • THE NSF CENTERS FOR NANOSCALE SCIENCE AND ENGINEERING
• Table 9 NSF NANOSCALE SCIENCE AND ENGINEERING CENTERS
  • THE NASA INSTITUTE FOR NANOELECTRONICS AND COMPUTING, PURDUEUNIVERSITY
  • UNIVERSITY ACTIVITY
• Table 10 MAJOR INTERNATIONAL RESEARCH INSTITUTIONS WITH NANOELECTRONICSEFFORTS
• Table 10 (CONTINUED)
• Table 11 NOTABLE SCIENTISTS INVOLVED IN NANOELECTRONICS RESEARCH
• Table 11 (CONTINUED)
  • INTERNATIONAL ACTIVITIES
    • EUROPE
    • IST's Future and Emerging Technologies (FET)
    • Nanotechnology Information Devices (NID) Initiative
    • Phantoms: Nanotechnology Network for Information Processingand Storage
• Table 12 EUROPEAN NID INITIATIVE RESEARCH PROJECTS RELATED TONANOELECTRONICS
• Table 12 (CONTINUED)
  • Institute of Nanotechnology
  • ASIA
  • R&D Association for Future Electron Devices
• Table 13 INDUSTRIAL PARTICIPANTS IN JAPAN'S R&D ASSOCIATION FOR FUTUREELECTRON DEVICES

TECHNOLOGY

• MATERIALS
  • CARBON NANOTUBES
  • Background
• Figure 3 STRUCTURE OF CARBON NANOTUBES
  • Fabrication
• Table 14 COMPARISON OF NANOTUBE PRODUCTION TECHNOLOGIES
  • New Developments
  • Catalyst-Free Nanotube Production
  • Growth of Nanotubes on Silicon Controlled
  • Selective Growth Process Developed
  • SEMICONDUCTOR NANOWIRES
  • Background
  • Fabrication
• Figure 4 SCHEMATIC OF SEMICONDUCTOR NANOWIRE GROWTH AND THE FORMATION OFAXIAL OR RADIAL HETEROSTRUCTURES
  • New Developments
  • Multishell Nanowire Heterostructures Formed
  • ORGANIC MOLECULES
  • Background
  • Fabrication
  • QUANTUM DOTS
  • Background
  • Fabrication
• Table 15 QUANTUM DOT FABRICATION METHODS
  • New Developments
  • Superlattice Quantum Dot Structures Produced
  • Size of Quantum Dots Tightly Controlled
  • Subnanoscale Gold Synthesized for Devices
  • Heat Treatment Forms Si Quantum Dots
  • Nanotubes Divided into Quantum Dots
  • PROCESSING TECHNOLOGIES
    • SELF-ASSEMBLY AND DIRECTED ASSEMBLY
    • Molecular Self-Assembly
    • Langmuir-Blodgett Technique
    • Self-Assembled Monolayer (SAM) Method
    • Chemical and Template Directed Assembly of Nanoparticles
    • Fluidic Directed Assembly
    • Biomolecule-Mediated Assembly
    • Diblock Copolymer Scaffold
    • DNA Scaffold
    • Protein Template
    • Peptide Molecule Template
    • NOVEL HIGH-RESOLUTION "SOFT" LITHOGRAPHY METHODS
    • Dip Pen Nanolithography (DPN)
    • Nano Imprint Lithography
    • Princeton University (Prof. Steve Chou) Approach
• Figure 5 SCHEMATIC OF NANOIMPRINT LITHOGRAPHY TECHNIQUE OF PRINCETONUNIVERSITY'S STEVE CHOU
  • Hewlett-Packard Approach
  • California NanoSystems Institute SNAP Approach
  • Quantum Dot-Based Lithography
  • PATENT ANALYSIS
    • GENERAL TRENDS
• Table 16 NUMBER OF NANOELECTRONICS-RELATED U.S. PATENTS ISSUED BY YEAR,1996-2002
• Figure 6 NUMBER OF NANOELECTRONICS-RELATED U.S. PATENTS ISSUED BY YEAR,1996-2002
  • TRENDS BY COUNTRY
• Table 17 NANOELECTRONICS-RELATED U.S. PATENTS, BY COUNTRY, 1996-2002(NUMBER AND PERCENT SHARE)
• Figure 7 NANOELECTRONICS-RELATED U.S. PATENTS, BY COUNTRY, 1996-2002 (%)
  • TRENDS BY TECHNOLOGY TYPE
• Table 18 NANOELECTRONICS-RELATED U.S. PATENTS, BY TECHNOLOGY TYPE,1996-2002 (NUMBER AND PERCENT SHARE)
• Figure 8 NANOELECTRONICS-RELATED U.S. PATENTS, BY TECHNOLOGY TYPE,1996-2002 (%)
• Table 19 INVENTIONS BASED ON CARBON OR ORGANIC MOLECULAR ELECTRONICSTECHNOLOGY, 1996-2002
• Table 19 (CONTINUED)
  • TRENDS BY ASSIGNEE
• Table 20 RECIPIENTS OF 2 OR MORE NANOELECTRONICS-RELATED U.S. PATENTS,1996-2002
  • Intellectual Property Leaders and Their Patented Technologies
  • Electronics and Telecommunications Research Institute (ETRI)
  • Fujitsu Ltd.
• Figure 9 FUJITSU'S PATENTED TETRAHEDRAL GROOVE STRUCTURE FOR A QUANTUM DOTFLOATING GATE MEMORY
  • Sony Corp.
  • Hewlett-Packard
• Figure 10 HP'S PLATEN FABRICATION METHOD AND IMPRINTING STEPS FORPATTERNING NANOSCALE WIRES
  • IBM Corp.
• Figure 11 IBM'S PATENTED QUANTUM DOT MEMORY DEVICE
• Figure 12 SCHEMATIC OF IBM'S CARBON NANOTUBE-BASED FET
  • Micron Technology Inc.
• Figure 13 FLOW CHART OF SINGLE ELECTRON MEMORY FABRICATION AS PATENTED BYMICRON TECHNOLOGY
  • Hynix Semiconductor, Inc., formerly Hyundai ElectronicsIndustries Co., Ltd.
• Figure 14 SIZE DISTRIBUTION OF QUANTUM DOTS FORMED IN HYNIXSEMICONDUCTOR'S PATENTED SET FABRICATION METHOD
  • TRENDS BY INVENTOR AFFILIATION
• Table 21 NANOELECTRONICS-RELATED U.S. PATENTS, BY AFFILIATION OFINVENTORS, 1996-2002
• Figure 15 NANOELECTRONICS-RELATED U.S. PATENTS, BY AFFILIATION OFINVENTORS, 1996-2002

IMPLEMENTATION AND CHALLENGES

• LOGIC DEVICES
  • CARBON NANOTUBE TRANSISTORS
  • Who's Who
• Table 22 WHO'S WHO IN CARBON NANOTUBE FET DEVELOPMENT
• Table 22 (CONTINUED)
  • Structure and Implementation
• Figure 16 SCHEMATICS OF CARBON NANOTUBE-BASED FIELD EFFECT TRANSISTORS
• Figure 16 (CONTINUED)
  • Fabrication Methods
  • Requirements and Challenges
  • Control Over Nanotube Positioning on Wafer
  • Control of Nanotube Size and Type
  • Theoretical Understanding
• Table 23 CHALLENGES FACING CARBON NANOTUBE FET TECHNOLOGY
  • New Technological Developments
  • Nanotube Transistors Reported to Outperform Silicon
  • Motorola Develops Parallel Process to Grow Nanotubes
  • QUANTUM DOT-BASED SINGLE ELECTRON TRANSISTORS
  • Who's Who
• Table 24 WHO'S WHO IN SINGLE ELECTRON TRANSISTOR DEVELOPMENT
• Table 24 (CONTINUED)
  • Structure and Implementation
• Table 25 REQUIREMENTS FOR A 2-D ARRAY OF SI QUANTUM DOTS TO SWITCH AT ROOMTEMPERATURE
  • Fabrication Methods
  • New Technological Developments
  • Conventional Semiconductor Processing Yields SET
  • SET From Chemically Synthesized Quantum Dots
  • SET From Chemically...(Continued)
  • Research Team Demonstrates Room T Silicon SET
  • Requirements and Challenges
  • Room Temperature Operation
• Table 26 COMPANIES AND INSTITUTIONS THAT HAVE DEMONSTRATED ROOMTEMPERATURE SINGLE ELECTRON DEVICES
  • Gain
  • Background Charges
  • High Output Impedance
• Table 27 CHALLENGES FACING SINGLE ELECTRON TRANSISTOR TECHNOLOGY
  • SEMICONDUCTOR NANOWIRE TRANSISTORS
  • Who's Who
• Table 28 WHO'S WHO IN NANOWIRE DEVICE DEVELOPMENT
  • Structure and Implementation
  • Fabrication Methods
  • Requirements and Challenges
  • Control Over Interfaces
  • Assembly into Complex Structures
  • Development of New Architectures
• Table 29 CHALLENGES FACING NANOWIRE DEVICE TECHNOLOGY
  • New Technological Developments
  • Striped Nanowires Produced at Berkeley
  • Multishell Nanowire Heterostructures Formed from Si and Ge
  • ORGANIC MOLECULAR ELECTRONIC DEVICES
  • Who's Who
• Table 30 WHO'S WHO IN MOLECULAR ELECTRONIC DEVICE DEVELOPMENT
  • Structure and Implementation
• Table 31 ADVANTAGES OF MOLECULES AS SWITCHES
  • Fabrication Methods
  • Requirements and Challenges
  • Construction of Three-Terminal Devices
  • Achievement of Gain
  • Interfacing with the Outside World
  • New Developments
  • Prototype Memory Cell Constructed from Self-Assembled Monolayers
  • MEMORY DEVICES
    • NANOTUBE/NANOWIRE AND MOLECULAR MEMORY ARRAYS
    • Who's Who
• Table 32 WHO'S WHO IN NANOWIRE OR MOLECULAR MEMORY ARRAY DEVELOPMENT
  • Structure and Implementation
  • Fabrication Methods
  • Requirements and Challenges
  • Interfacing Devices with Outside World
  • Identification and Characterization of Molecules
  • Realizing a 3-D Architecture
• Table 33 REQUIREMENTS OF MOLECULAR MEMORY ARRAY DEVICES
  • New Technological Developments
  • Nanotube Memory Formed Using Conventional SemiconductorProcessing
  • HP Builds Ultrahigh Density Molecular Memory
• Figure 17 SCHEMATIC OF HP'S 64-BIT LABORATORY PROTOTYPE MOLECULAR MEMORYARRAY
  • SILICON NANOCRYSTAL MEMORY
  • Who's Who
• Table 34 WHO'S WHO IN SILICON NANOCRYSTAL MEMORY DEVELOPMENT
  • Structure and Implementation
  • Fabrication Methods
• Table 35 FABRICATION TECHNIQUES EXPLORED FOR SILICON NANOCRYSTALNONVOLATILE MEMORIES
  • New Technological Developments
  • Motorola Demonstrates 4-Megabit Nanocrystal Test Memory
  • Nanocrystals Allow Integration of Two Memory Types
  • Requirements and Challenges
  • Sufficient Nanocrystal Areal Density
  • Control of Nanocrystal Size, Uniformity
  • Control of Tunnel Oxide Thickness
  • Process Simplicity and Integration
  • SPINTRONIC DEVICES: MAGNETIC RANDOM ACCESS MEMORY (MRAM)
  • Who's Who
• Table 36 COMPANIES ACTIVE IN MRAM DEVELOPMENT
  • Structure and Implementation
• Figure 18 SCHEMATIC OF MRAM STORAGE DEVICE STRUCTURE
• Figure 19 SCHEMATIC OF MRAM ARCHITECTURE
  • Fabrication Methods
  • New Technological Developments
  • Magneto-Thermal MRAM Pursued
  • Requirements and Challenges
  • Film Thickness Uniformity
  • Superparamagnetic Limit
  • Minimization of Drive Currents
  • Integration with Semiconductor Fabrication

OUTLOOK AND ROADMAP

• INTRODUCTION
• NANOELECTRONIC MEMORY TECHNOLOGIES
  • SILICON NANOCRYSTAL MEMORIES
  • MRAM
  • MOLECULAR ELECTRONIC MEMORIES
  • CARBON NANOTUBE MEMORIES
• Table 37 COMPARISON OF NANOELECTRONIC MEMORY TECHNOLOGIES
  • SEMICONDUCTOR NANOWIRE MEMORIES
  • NANOELECTRONIC LOGIC TECHNOLOGIES
    • MOLECULAR SWITCHES
• Table 38 COMPARISON OF NANOELECTRONIC TRANSISTOR TECHNOLOGIES
  • CARBON NANOTUBE AND SEMICONDUCTOR NANOWIRE FETS
  • Carbon Nanotube and Semiconductor...(Continued)
  • SINGLE ELECTRON TRANSISTORS
• Table 39 APPLICATIONS FOR SINGLE-ELECTRON TRANSISTORS
  • NEW LOGIC ARCHITECTURES
• Table 40 ATTRIBUTES OF NEXT-GENERATION NANOCOMPUTING ARCHITECTURE
  • Programmable Logic Arrays
  • Implementation
  • Components
• Table 41 COMPARISON OF POSSIBLE NANOELECTRONIC LOGIC ARCHITECTURES
  • Quantum Dot Cellular Automata (QCA)
  • Implementation
  • Components
  • SUMMARY AND CONCLUSIONS
    • CURRENT SEMICONDUCTOR CHIP MARKET
• Table 42 GLOBAL MARKET FOR MEMORY PRODUCTS, THROUGH 2007 ($ MILLIONS)
• Table 43 GLOBAL INTEGRATED CIRCUIT MARKET, THROUGH 2006 ($ BILLIONS)
  • PROJECTED MARKET FOR NANOELECTRONIC DEVICES
• Table 44 POTENTIAL MARKET FOR NANOELECTRONIC MEMORY AND LOGIC PRODUCTS,THROUGH 2013 ($ BILLIONS)
• Figure 20 POTENTIAL MARKET FOR NANOELECTRONIC MEMORY AND LOGIC PRODUCTS,2003-2013 ($ BILLIONS)
  • NANOELECTRONIC MEMORY PRODUCTS
• Table 45 TIME FRAME FOR INTRODUCTION OF NANOELECTRONIC MEMORY PRODUCTS,2003-2017
• Figure 21 POTENTIAL IMPACT VS. COMMERCIAL VIABILITY OF NANOELECTRONICMEMORY TECHNOLOGIES
• Figure 22 COMMERCIAL STATUS OF NANOELECTRONIC MEMORY TECHNOLOGIES IN 2003
• Figure 23 COMMERCIAL STATUS OF NANOELECTRONIC MEMORY TECHNOLOGIES IN 2008
• Figure 24 COMMERCIAL STATUS OF NANOELECTRONIC MEMORY TECHNOLOGIES IN 2013
  • NANOELECTRONIC LOGIC PRODUCTS
• Table 46 TIME FRAME FOR INTRODUCTION OF NANOELECTRONIC LOGIC PRODUCTS,2003-2017
• Figure 25 POTENTIAL IMPACT VS. COMMERCIAL VIABILITY OF NANOELECTRONICLOGIC TECHNOLOGIES
• Figure 26 COMMERCIAL STATUS OF NANOELECTRONIC LOGIC TECHNOLOGIES IN 2003
• Figure 27 COMMERCIAL STATUS OF NANOELECTRONIC LOGIC TECHNOLOGIES IN 2008
• Figure 28 COMMERCIAL STATUS OF NANOELECTRONIC LOGIC TECHNOLOGIES IN 2013

APPENDIX

• COMPANY CONTACT INFORMATION
  • CALIFORNIA MOLECULAR ELECTRONICS CORP.
  • COATUE CORP.
  • IBM T.J. WATSON RESEARCH LABORATORY
  • HEWLETT-PACKARD LABS
  • MITRE CORP.
  • MOLECULAR ELECTRONICS CORP.
  • MOTOROLA SEMICONDUCTOR PRODUCTS SECTOR
  • NANOINK INC.
  • NANONEX CORP
  • NANOSYS, INC.
  • NANTERO, INC.
  • QUANTUM LOGIC DEVICES
  • ROLLTRONICS
  • THIN FILM ELECTRONICS
  • ZETTACORE, INC.
• U.S. PATENT COMPILATION
• Table 47 COMPILATION OF U.S. PATENTS RELATED TO NANOELECTRONICS, 1996-2002
• Table 47 (CONTINUED)
• Table 47 (CONTINUED)
• Table 47 (CONTINUED)
• Table 47 (CONTINUED)
• Table 47 (CONTINUED)
• Table 47 (CONTINUED)

LIST OF TABLES

Summary Table:
POTENTIAL MARKET FOR NANOELECTRONIC MEMORY AND LOGIC PRODUCTS, 2003-2013 ($BILLIONS)

Table 1 INCREASE IN TRANSISTORS PER CHIP BY YEAR

Table 2 PROJECTED CHANGE IN CRITICAL FEATURE SIZES OF INTEGRATED CIRCUITS,2002-2016 (NM)

Table 3 OBSTACLES TO CONTINUED TRANSISTOR SCALING

Table 4 TECHNOLOGIES LIKELY TO EXTEND CONVENTIONAL TRANSISTOR TECHNOLOGY

Table 5 TIMELINE OF IMPORTANT EVENTS IN THE DEVELOPMENT OF NANOELECTRONICS

Table 6 WHO'S WHO IN THE NANOELECTRONICS BUSINESS

Table 7 COMPARISON OF NANOELECTRONICS START-UP COMPANIES

Table 8 PARTICIPANTS AND PROJECTS IN DARPA'S MOLETRONICS PROGRAM

Table 9 NSF NANOSCALE SCIENCE AND ENGINEERING CENTERS

Table 10 MAJOR INTERNATIONAL RESEARCH INSTITUTIONS WITH NANOELECTRONICSEFFORTS

Table 11 NOTABLE SCIENTISTS INVOLVED IN NANOELECTRONICS RESEARCH

Table 12 EUROPEAN NID INITIATIVE RESEARCH PROJECTS RELATED TONANOELECTRONICS

Table 13 INDUSTRIAL PARTICIPANTS IN JAPAN'S R&D ASSOCIATION FOR FUTUREELECTRON DEVICES

Table 14 COMPARISON OF NANOTUBE PRODUCTION TECHNOLOGIES

Table 15 QUANTUM DOT FABRICATION METHODS

Table 16 NUMBER OF NANOELECTRONICS-RELATED U.S. PATENTS ISSUED BY YEAR,1996-2002

Table 17 NANOELECTRONICS-RELATED U.S. PATENTS, BY COUNTRY, 1996-2002(NUMBER AND PERCENT SHARE)

Table 18 NANOELECTRONICS-RELATED U.S. PATENTS, BY TECHNOLOGY TYPE,1996-2002 (NUMBER AND PERCENT SHARE)

Table 19 INVENTIONS BASED ON CARBON OR ORGANIC MOLECULAR ELECTRONICSTECHNOLOGY, 1996-2002

Table 20 RECIPIENTS OF 2 OR MORE NANOELECTRONICS-RELATED U.S. PATENTS,1996-2002

Table 21 NANOELECTRONICS-RELATED U.S. PATENTS, BY AFFILIATION OFINVENTORS, 1996-2002

Table 22 WHO'S WHO IN CARBON NANOTUBE FET DEVELOPMENT

Table 23 CHALLENGES FACING CARBON NANOTUBE FET TECHNOLOGY

Table 24 WHO'S WHO IN SINGLE ELECTRON TRANSISTOR DEVELOPMENT

Table 25 REQUIREMENTS FOR A 2-D ARRAY OF SI QUANTUM DOTS TO SWITCH AT ROOMTEMPERATURE

Table 26 COMPANIES AND INSTITUTIONS THAT HAVE DEMONSTRATED ROOMTEMPERATURE SINGLE ELECTRON DEVICES

Table 27 CHALLENGES FACING SINGLE ELECTRON TRANSISTOR TECHNOLOGY

Table 28 WHO'S WHO IN NANOWIRE DEVICE DEVELOPMENT

Table 29 CHALLENGES FACING NANOWIRE DEVICE TECHNOLOGY

Table 30 WHO'S WHO IN MOLECULAR ELECTRONIC DEVICE DEVELOPMENT

Table 31 ADVANTAGES OF MOLECULES AS SWITCHES

Table 32 WHO'S WHO IN NANOWIRE OR MOLECULAR MEMORY ARRAY DEVELOPMENT

Table 33 REQUIREMENTS OF MOLECULAR MEMORY ARRAY DEVICES

Table 34 WHO'S WHO IN SILICON NANOCRYSTAL MEMORY DEVELOPMENT

Table 35 FABRICATION TECHNIQUES EXPLORED FOR SILICON NANOCRYSTALNONVOLATILE MEMORIES

Table 36 COMPANIES ACTIVE IN MRAM DEVELOPMENT

Table 37 COMPARISON OF NANOELECTRONIC MEMORY TECHNOLOGIES

Table 38 COMPARISON OF NANOELECTRONIC TRANSISTOR TECHNOLOGIES

Table 39 APPLICATIONS FOR SINGLE-ELECTRON TRANSISTORS

Table 40 ATTRIBUTES OF NEXT-GENERATION NANOCOMPUTING ARCHITECTURE

Table 41 COMPARISON OF POSSIBLE NANOELECTRONIC LOGIC ARCHITECTURES

Table 42 GLOBAL MARKET FOR MEMORY PRODUCTS, THROUGH 2007 ($ MILLIONS)

Table 43 GLOBAL INTEGRATED CIRCUIT MARKET, THROUGH 2006 ($ BILLIONS)

Table 44 POTENTIAL MARKET FOR NANOELECTRONIC MEMORY AND LOGIC PRODUCTS,THROUGH 2013 ($ BILLIONS)

Table 45 TIME FRAME FOR INTRODUCTION OF NANOELECTRONIC MEMORY PRODUCTS,2003-2017

Table 46 TIME FRAME FOR INTRODUCTION OF NANOELECTRONIC LOGIC PRODUCTS,2003-2017

Table 47 COMPILATION OF U.S. PATENTS RELATED TO NANOELECTRONICS, 1996-2002 

LIST OF FIGURES

Summary Figure:
POTENTIAL MARKET FOR NANOELECTRONIC MEMORY AND LOGIC PRODUCTS, 2003-2013 ($BILLIONS)

Figure 1 MOORE'S LAW ILLUSTRATED

Figure 2 IMPACT OF DOPANT DISTRIBUTION AT DIFFERENT SIZE SCALES

Figure 3 STRUCTURE OF CARBON NANOTUBES

Figure 4 SCHEMATIC OF SEMICONDUCTOR NANOWIRE GROWTH AND THE FORMATION OFAXIAL OR RADIAL HETEROSTRUCTURES

Figure 5 SCHEMATIC OF NANOIMPRINT LITHOGRAPHY TECHNIQUE OF PRINCETONUNIVERSITY'S STEVE CHOU

Figure 6 NUMBER OF NANOELECTRONICS-RELATED U.S. PATENTS ISSUED BY YEAR,1996-2002

Figure 7 NANOELECTRONICS-RELATED U.S. PATENTS, BY COUNTRY, 1996-2002 (%)

Figure 8 NANOELECTRONICS-RELATED U.S. PATENTS, BY TECHNOLOGY TYPE,1996-2002 (%)

Figure 9 FUJITSU'S PATENTED TETRAHEDRAL GROOVE STRUCTURE FOR A QUANTUM DOTFLOATING GATE MEMORY

Figure 10 HP'S PLATEN FABRICATION METHOD AND IMPRINTING STEPS FORPATTERNING NANOSCALE WIRES

Figure 11 IBM'S PATENTED QUANTUM DOT MEMORY DEVICE

Figure 12 SCHEMATIC OF IBM'S CARBON NANOTUBE-BASED FET

Figure 13 FLOW CHART OF SINGLE ELECTRON MEMORY FABRICATION AS PATENTED BYMICRON TECHNOLOGY

Figure 14 SIZE DISTRIBUTION OF QUANTUM DOTS FORMED IN HYNIXSEMICONDUCTOR'S PATENTED SET FABRICATION METHOD

Figure 15 NANOELECTRONICS-RELATED U.S. PATENTS, BY AFFILIATION OFINVENTORS, 1996-2002

Figure 16 SCHEMATICS OF CARBON NANOTUBE-BASED FIELD EFFECT TRANSISTORS

Figure 17 SCHEMATIC OF HP'S 64-BIT LABORATORY PROTOTYPE MOLECULAR MEMORYARRAY

Figure 18 SCHEMATIC OF MRAM STORAGE DEVICE STRUCTURE

Figure 19 SCHEMATIC OF MRAM ARCHITECTURE

Figure 20 POTENTIAL MARKET FOR NANOELECTRONIC MEMORY AND LOGIC PRODUCTS,2003-2013 ($ BILLIONS)

Figure 21 POTENTIAL IMPACT VS. COMMERCIAL VIABILITY OF NANOELECTRONICMEMORY TECHNOLOGIES

Figure 22 COMMERCIAL STATUS OF NANOELECTRONIC MEMORY TECHNOLOGIES IN 2003

Figure 23 COMMERCIAL STATUS OF NANOELECTRONIC MEMORY TECHNOLOGIES IN 2008

Figure 24 COMMERCIAL STATUS OF NANOELECTRONIC MEMORY TECHNOLOGIES IN 2013

Figure 25 POTENTIAL IMPACT VS. COMMERCIAL VIABILITY OF NANOELECTRONICLOGIC TECHNOLOGIES

Figure 26 COMMERCIAL STATUS OF NANOELECTRONIC LOGIC TECHNOLOGIES IN 2003

Figure 27 COMMERCIAL STATUS OF NANOELECTRONIC LOGIC TECHNOLOGIES IN 2008

Figure 28 COMMERCIAL STATUS OF NANOELECTRONIC LOGIC TECHNOLOGIES IN 2013