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SUMMARY
Abstract
This report spotlights the most innovative processors of 2005 in the
Desktop/Mobile PC and Server categories. Only chips that were released for
production shipments during the calendar year were eligible to be selected as
nominees. The nominations were based on the best public information available
to our analysts in December 2005.
The report begins with two award articles naming the winners of the
Microprocessor Report Analysts' Choice Awards for 2005. What follows is a
gathering of Microprocessor Report articles published throughout the year on
the processors nominated.
TABLE OF CONTENTS
- Introduction
- MPR's Best PC Processor of 2005
- Dual-Core and Mobile Processor Architectures Change the Playing Field
- MPR's Best Server of 2005
- Choice Reflects the Best-Balanced Processor
- AMD Changes Its Strategy
- AMD Adds Seven Years of Support to Selected Opterons.
- Shift in Server Designs
- One More Step in Server Equation
- On the Road to Many-Core µPs
- Cores Proliferate at Intel's Spring '05 Developer Forum
- What Makes a Dual-Core Processor?
- The Platforms for the Dual Core
- Yonah and Montecito Take Dual Core to Heart
- Many-Core Processors in the Future
- AMD's Turion 64 Mobile Processor
- An AMD64 Processor by Any Other Name
- How Does Turion 64 Stack Up?
- Reading Between the Lines
- Day at the Races
- AMD and Intel Rush Dual-Core Introductions
- Is the Market Ready?
- Expect More Announcements Shortly
- Multicore Showdown
- Multicore Moving from Embedded to Servers to Clients
- Multicore: The Early Years
- Modern Embedded Applications
- Servers Serve Up Robust Cores
- And Now It's the PC's Turn
- Multicore Design Issues
- Program Support for Multiple Cores
- The Scorecard So Far
- IDF Fall 2005: More Cores, Less Power
- Intel's Next Generation Microarchitecture and Revenge of the CISC
- Intel's New Microarchitecture Didn't Surprise
- Intel Next Generation Based on Yonah
- More Clues to Power Savings
- Intel to Take IA-32 Even Lower
- IDF Coverage Part II
- Intel Shifts Product Line to Mobile Architecture
- Mobile, Mobile, and More Mobile
- What Lies Ahead
- Yonah Does Dual-Core Right
- More Details From IDF Fall 2005
- Yonah by the Numbers
- Core Improvements
- IBM's Double-Shot of PowerPC
- The Long-Anticipated Dual-Core PowerPC 970MP Arrives
- POWER4 Microarchitecture Intact
- Playing Fair With the I/O
- Managing the Dual-Core Power
- The Power to Perform
- SPARC's Still Going Strong
- Fujitsu's New Products Increase Cores, Threads; Sun's Niagara Near
- RAS by Any Other Name
- SPARC Doubles Down Again in 65nm
- Sun Makes Its Own Appearance
- Ringside for 2006 Dual-Core Fights
- A Review of the Dual-core Battles Between AMD and Intel
- Intel Touts Dual- and Multicore Development
- AMD Slips Into Silence
- The Action Begins With Desktop Processors
- Mobile Processor Featured in Bout Two
- Servers Featured in the Main Event
- Taking Score
- Sun's Niagara Begins CMT Flood
- The Sun UltraSPARC T1 Processor Released
- Niagara 2 Makes the Leap to True SoC
- Some Tuning Required
- Sun Will Release Parts of Niagara Design
- Competitors Take Swipes at Niagara
- When Good Products Get Bad Marketing
- List of Tables
- Table 1. The candidates for best PC processor
- Table 2. AMD Opterons offered with the longevity program
- Table 3. Specifications for the New Turion 64 processors
- Table 4. Mobile Athlon 64 vs. Turion 64 ML
- Table 5. Turion 64 vs. Pentium M
- Table 6. This table provides a broad comparison of multicore embedded
processors
- Table 7. Intel dual-core line-up based on the Banias architecture
- Table 8. IDIV speed enhancements in Yonah
- Table 9. Average power values for the PPC 970MP
- List of Figures
- Figure 1. Die photo of Intel Core Duo processor
- Figure 2. VoIP subscriber growth
- Figure 3. The Smithfield (left) and Presler processors generate two
bus-interface loads on the Pentium 4 bus, unlike a single-core processor
- Figure 4. The bus interface for the dual-core Xeon processor, code-named
Paxville, has an integrated bus interface, limiting the bus loading to one
load.
- Figure 5. A dual-processor system based on the dual-core Dempsey
processor will connect to the Blackford chip set with two independent buses
- Figure 6. The quad-processor system with the Paxville processor
- Figure 7. Block diagram and die photo of the Turion 64 processor
- Figure 8. AMD Opteron 840 processor block diagram and die photo
- Figure 9. Intel Pentium EE block diagram and die photo
- Figure 10. The various on-chip interconnect strategies
- Figure 11. The figure on the left shows an example of user-processing
demand varying over time
- Figure 12. Intel public processor roadmap
- Figure 13. Yonah die picture from IDF Fall '05
- Figure 14. The two cores in Yonah can independently change the C1 to C3
power state
- Figure 15. The PowerPC 970MP microarchitecture remains largely intact
but with the improvement of a larger L2 cache per core
- Figure 16. The IBM PPC970MP die layout
- Figure 17. Both of the cores vary voltage and frequency in unison
- Figure 18. For more-aggressive power savings, IBM has the nap and deeper
nap modes
- Figure 19. Fujitsu's latest SPARC64 roadmap. The SPARC64 VI appears to
ship in 2H06 and the SPARC64 VI+ in early 2008
- Figure 20. The SPARC64 VI processor has extra sets of registers that are
used by the current register window and are backed by the set of two GPR
register blocks
- Figure 21. Introducing threads allows the processor to continue to scale
and can lead to a gain of up to 20%. This chart shows four threads as the
point where scaling levels off, but while the SPARC64 VI has only two cores,
the model is for a dual-CPU system
- Figure 22. Intel's desktop PC processor roadmap
- Figure 23. Intel Mobile PC processor roadmap
- Figure 24. Intel Xeon server-processor roadmap
- Figure 25. Intel Itanium server-processor roadmap
- Figure 26. The packaged UltraSPARC T1 processor, formerly code-named
Niagara
- Figure 27. The Niagara 1 block diagram
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