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SUMMARY
The ultimate report to weight the strength and weakness of existing 3D ICs
technologies, and see who is doing what in term of 3D packaging among the key
players
The technical issues for innovative 3D packaging at the wafer level are close
to be solved.
Yole's latest report highlights the market drivers for 3D packaging
technologies, the status of developments, how it will impact the semiconductor
food chain. It covers as well equipments market forecasts and technical
analyses of the different solutions with extensive exclusive technical
explanation, figures and abstracts.
3D integration will affect the IC, MEMS and image sensors markets!
Semiconductor chips face constant pressure for increased performances while
still decreasing their size and at the same time their packages must be able
to accommodate new functionalities. The ever-expanding consumer electronics
market is a particularly strong driver of packaging innovations such as 3D
ICs. Today wire bonding is limited in density and performances so 3D stacking
with micro-vias (or TSV, "through-Si vias") seems to be unavoidable in the
future for miniaturization first and increased performances after.
3D integration will use technologies originally developed for MEMS technology
but for different markets. In our report, we have analyzed that portable
applications are a strong market driver for 3D integration. Stacking memories,
stacking memories and logic, image sensors with μP and FPGAs will be the
first mass market applications. In 2010, we forecast that 1 billion of Flash
memories will be stacked with TSVs
3D-ICs: the technical challenges are close to be overcome
3D is the most "integrated" approach and is an enabling technology platform
applicable to digital and mixed signal electronics, wireless, electro-optical,
MEMS, sensors, smart imagers, displays and other devices. There are however
strong challenges. They are: thermal management, reliable co-design and
simulation tools, industrial wafer-to-wafer bonding tools, low-cost
through-wafer via structures and via fill processes. In our report we have
analyzed and compared the different technical solutions
TABLE OF CONTENTS
List of figures
Acronyms & definitions
Objectives of the report
Advanced packaging challenges
- Packaging evolution
- From 2 D to 3D
- Trends for stacking
- SoC, SiP and 3D IC
- 3D interconnect technology trend
3D IC markets
- Definition of TSVs
- Market drivers
- Memories
- Memories segmentation
- Where TSVs will be use
- Flash memory market
- Roadmap for 3D IC players
- Image sensors
- TSVs for image sensors
- Roadmap
- Examples
- MEMS
Packaging supply chain
- Supply chain of packaging players
- Impact on business models
Equipment and materials market forecasts
- Hypothesis
- Market forecasts
3D IC - Scenarios for stacking chips
- Different approaches for going to 3D
- 3D IC - Interconnect technologies
- Bonding processes
- Overview of bonding technologies
- Via-first vs. via-last
- TSVs manufacturing
- Cost comparison
- DRIE vs. laser
- Vias characteristics
- Vias filling
- TSVs vs. wire bonding
- W2W versus C2W
- Bonding cost comparison
Handling of thin die/wafers issues
Grinding/thinning concepts
Examples of 3D developments
Conclusions on 3D ICs
Annexes
- Packaging definitions
- Bonding cost comparison
- List of interviewed companies
- Yole Developpement presentation
- Presentation of Yole's Multi-Customer Action
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